As shown in FIG. 1, a conventional flyback converter 100 comprises a transformer TX having a primary winding Lp connected in serial with a power switch SW between a power input Vin and ground GND, a control circuit 102 to switch the power switch SW to generate a secondary current Is flowing through a secondary winding Ls of the transformer TX so as to charge a capacitor Cout and subsequently generate an output voltage Vout, and an optical coupler 104 composed of light emitting diode D2 and transistor 108 and a compensation network 106 to feed back the output voltage Vout to a feedback pin FB of the control circuit 102 for regulating the output voltage Vout. When the power switch SW is on, the primary winding Lp has a primary current Ip flowing therethrough, and a sensing pin CS of the control circuit 102 receives a voltage Vcs across a resistor Rcs so as to sense the primary current Ip. In the control circuit 102, a waveform generator 110 provides a clock CLK and a sawtooth signal 111 whose DC level is shifted according to the signal from the feedback pin FB, a comparator 112 generates a signal S1 for an OR gate 114 in response to the voltage Vcs and the level-shifted sawtooth signal 111. If the comparison signal S1 transits to high, the OR gate 114 resets a flip-flop 116 and thereby turns off the power switch SW such that the primary current Ip is off. To prevent from excessive output power when overload or short circuit happens, the flyback converter 100 is provided with an output power limiter for limiting the output power of the flyback converter 100. The output power limiter includes a limit signal generator 120 to provide a current limit signal Vcl and a comparator 122 to compare the current limit signal Vcl with the current sense signal Vcs to determine a comparison signal S2. If the current sense signal Vcs is greater than the current limit signal Vcl, the comparison signal S2 will reset the flip-flop 116 so as to turn off the power switch SW.
FIG. 2 graphically illustrates the relation between the output voltage Vout and the output current lout of the flyback converter 100. If the output current lout does not reach a constant power limit A, the flyback converter 100 operates in a constant voltage mode so as to maintain a stable output voltage Vout. Once the output current lout reaches the constant power limit A, the flyback converter 100 will enter into a constant power mode to maintain the output power at a constant value by reducing the output voltage Vout with the increased output current lout. For simplicity, in case the efficiency is not taken into consideration, the output power Pout shall be equal to the input power Pin asPout=Pin=(1/2)×Lp×(Ipk2−Ivalley2)×fs,  [EQ-1]where Ipk is the peak value of the primary current Ip, Ivalley is the valley value of the primary current Ip, and fs is the switching frequency of the power switch SW. As shown by the equation EQ-1, the peak value Ipk and the valley value Ivalley of the primary current Ip will influence the output power Pout.
FIG. 3 illustrates a traditional method for output power limit for a power converter, in which waveforms 124 and 126 represent the current sense signal Vcs and current limit signal Vcl respectively, and the dot line represents the total magnetic current of the transformer TX. In this scheme, the current limit signal Vcl is constant as shown by the waveform 126, and when the current sense signal Vcs increases to reach the current limit signal Vcl, indicating that the primary current Ip is so large that the output power Pout reaches the upper threshold, the control circuit 102 will turn off the power switch SW to limit the output power Pout. However, there is always a certain delay time Tp between the time that the current sense signal Vcs reaches the current limit signal Vcl and the time that the power switch SW is turned off. Such delay time Tp primarily results from propagation delay caused by logic delay and gate driver delay. During this delay time Tp, since the primary current Ip is still on, the current sense signal Vcs will keep increasing until the power switch SW is turned off. Generally, the delay time Tp is very short and therefore the effect it causes is not obvious when the flyback converter 100 operates with low frequency. However, the effect caused by the delay time Tp becomes more obvious when the operation frequency of the flyback converter 100 increases.
Since the delay time Tp primarily results form logic delay and gate driver delay, it will be approximately constant if identical power switch SW is used. When the flyback converter 100 is regulated, the excess output power Pout is eliminated by the feedback compensation. However, in some particular situations, such as overload, a constant current limit signal Vcl will lead to diverse values of the output power Pout and subsequently generate diverse values of the output voltage Vout. FIG. 4 illustrates the current sense signals Vcs generated under different input voltages Vin, in which waveform 128 represents the current limit signal Vcl, waveform 130 represents the current sense signal Vcs under a low input voltage Vin, and waveform 132 represents the current sense signal Vcs under a high input voltage Vin. When the input voltage Vin is relatively low, the increasing speed of the primary current Ip is lower, and thereby the increasing speed of the current sense signal Vcs is lower correspondingly, as shown by the waveform 130. When the input voltage Vin is higher, the increasing speed of the primary current Ip is higher, and thereby the increasing speed of the current sense signal Vcs is higher correspondingly, as shown by the waveform 132. Thus, under a constant delay time Tp, a high input voltage Vin causes a higher peak value Ipk of the primary current Ip, and according to the equation EQ-1, the higher peak value Ipk will generate a higher output power Pout. As shown in FIG. 4, if the current limit signal Vcl is constant, different input voltages Vin will generate different peak values Ipk and thus, a flyback converter cannot provide a constant output power Pout.
To remedy the problem that different input voltage Vin generate different output power Pout, a proposed method senses the input voltage Vin to modify the current limit signal Vcl. However, such strategy requires an additional sense circuit to sense the input voltage Vin. U.S. Pat. No. 6,674,656 to Yang et al. proposed a PWM controller having a saw-limiter for output power limit without sensing input voltage. FIG. 5 illustrates this method, in which waveform 134 represents the current limit signal Vcl, waveform 136 represents the current sense signal Vcs under a low input voltage, and waveform 138 represents the current sense signal Vcs under a high input voltage. A sawtooth waveform is used to generate a linear current limit signal Vcl as shown by the waveform 134 and thus, the current sense signal Vcs generated by a lower input voltage will have a higher current limit level as shown by the waveform 136, and the current sense signal Vcs generated by a higher input voltage will have a lower current limit level as shown by the waveform 138. Thereupon, a same peak value can be achieved and the output power is somehow stabilized. However, the relation between the current limit signal Vcl and the input voltage Vin is not exactly linear and therefore the Yang method only achieves a rough constant output power limit.